1. Background of the Invention
This invention relates generally to data processors, and, more particularly, to a microprocessor wherein a bus cycle may be retried upon detection of a bus error.
2. Description of the Prior Art
Recent improvements in MOS semiconductor technology have resulted in advances in large scale integrated circuit microprocessors. The latest generation of LSI microprocessors is an order of magnitude more powerful than the previous generation introduced three or four years ago. The latest generation of microprocessors have 16 bit data paths and 16 bit arithmetic capability, and they directly address multiple-megabyte memories. In terms of functional capability and speed, they will out perform all but the high-end models of current 16 bit minicomputers.
LSI microprocessor design is now at a stage where better implementation techniques are required in order to control complexity and meet tight design schedules. One technique for achieving these goals is to use microprogramming for controlling the processing. Some of the traditionally claimed benefits of microprogramming are, for example, regularity (to decrease complexity), flexibility (to ease design changes), and reduced design costs.
It is well known to provide a data processing system which includes a software capability for processing bus transfer errors. However, such software capabilities are both complex and expensive and, as such, are not suitable for microprocessor applications. Furthermore, for simple problems such as parity errors on transfers, the software approach to correcting bus errors is prohibitive in terms of the amount of time required before the processor can retry the cycle.